As DRAMs increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. A principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three dimensional cell capacitors, such as trenched or stacked capacitors. This invention concerns stacked capacitor cell constructions.
With the conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Problems associated with the prior art are described with reference to FIGS. 1-3. FIG. 1 illustrates a semiconductor wafer fragment 10 comprised of a bulk substrate 12, a pair of adjacent word lines 14, 16, and field oxide region 18. The illustrated region between word lines 14 and 16 will be utilized for formation of a stacked capacitor construction. The area to the left of word line 14 will be utilized for a bit line contact.
Substrate 12 is comprised of a p-type material having a p-type dopant concentration of approximately 2.times.10.sup.15 atoms/cm.sup.3, with the intent being to form n-channel transistors utilizing word lines 14 and 16. Such word lines are comprised of a conventional construction of gate oxide 20, conductively doped polysilicon 22, a more highly conductive silicide layer 24, and an overlying insulating oxide cap 26. Pairs 28, 30 of anisotropically etched side wall spacers are provided about outer edges of word lines 14 and 16. Such function to insulate the sides of word lines 14 and 16, and in the course of processing provide desired spacings for formation of LDD regions. The illustrated double side wall spacer is utilized to facilitate formation of the desired LDD construction for proper circuit operation.
More specifically and prior to any spacer formation, a p-type LDD halo implant at a dose of approximately 4.times.10.sup.12 atoms/cm.sup.2 is provided into bulk substrate 12 to provide halo regions 32. Such constitute a part of an LDD construction. Thereafter, a layer of insulating material, typically SiO.sub.2, is deposited atop the wafer and anisotropically etched to form spacer pairs 28. Thereafter, an n-type LDD implant is conducted at a typical dose of 1.5.times.10.sup.13 atoms/cm.sup.2 to produce regions 34, as shown. Such constitute a further aspect of a LDD construction, as is known by people of skill in the art. Thereafter, another layer of insulating material, such as SiO.sub.2, is deposited and anisotropically etched to produce spacer pairs 30. Thereafter, a heavy n+ implant, typically at a dose of 8.times.10.sup.15 atoms/cm.sup.2, is provided to form high concentration n+ regions 36. Such regions 36 will be utilized to connect with bit lines and for capacitor formation.
The process typically next continues by depositing and planarizing a layer 38 of insulating material. Referring to FIG. 2, insulating layer 38 is typically patterned and etched to produce a contact opening 40 which extends downwardly to active region 36 between word lines 14 and 16 for ultimate formation of a capacitor construction. It would of course be desirable, with a principle goal of circuit density maximization, to space the illustrated word line 14 as close as possible to the field oxide region, and correspondingly allow all the word lines and accompanying circuitry to be crowded closer together. However, added space must be provided to allow for inevitable mask misalignment which might otherwise lead to destruction of the circuit. Presently, this added space for misalignment requires an extra 0.15 micron beyond that which would otherwise be required if photolithographic techniques could be avoided in providing contacts to active area 36.
Referring to FIG. 3, a layer 42 of polysilicon is deposited and patterned as illustrated to define isolated capacitor storage nodes. Polysilicon layer 42 is doped with an electrically conductive enhancing impurity to render such region electrically conductive. Thereafter, a thin capacitor dielectric layer 44, followed by a thicker capacitor cell polysilicon layer 46, is deposited to complete construction of the capacitor.
It would be desirable to improve upon these and other aspects of three dimensional stacked capacitor constructions, and to provide techniques which do not require use of insulating layer 38 and its associated buried contact mask.